Trenches are conventionally formed in a semiconductor substrate by etching into the substrate. The etch chemistry results in the trench width being directly proportional to the trench depth so that deeper trenches tend to be wider than shallower trenches. For applications that require low channel resistance, e.g. small signal, low voltage FET, etc., hexagonal, triangular and square trench geometries are commonly employed to increase the channel (width) density. Such trench geometries have inhomogeneous trench depth distribution, corresponding to process window reduction, reliability degradation and/or an undesirable tradeoff between on-state resistance (Ron) and breakdown voltage. Vertical multi-poly electrode FETs require multiple fill-in, recess, and oxidation/CVD processes to stack up multiple poly electrodes, adding to process complexity and cost. It is also difficult to control the thickness and quality of the inter-poly dielectric, which negatively affects yield rate and device reliability. Furthermore, manufacturing cost increases with larger thermal budget and process complexity. Many applications require trench alignment with a specific silicon region. A ‘safe’ margin is usually required to inhibit the p-body from overlapping the vertical gate electrode, resulting in higher ohmic resistance. The additional margin also results in lower Miller capacitance (Cgd) which reduces switching frequency.
In the manufacturing process, it is difficult to control the implant through round trench corners which can cause inhomogeneous dopant distribution. In some region on the chip, the geometric layout and implant profile could possibly have non-negligible discrepancies with respect to the rest of the chip area. Such non-negligible discrepancies can lead to e.g. a weak point which restricts the design rules and requires precise process control or extra process steps to mitigate the effect.
Shrinking die (chip) size requirements exacerbates these problems, while the associated complex process and design rule requirements frustrate FET development, especially in low voltage and/or switching applications, resulting in long time-to-market. In some cases, a strip-like trench has been used to mitigate the trench depth variation problem even though each strip trench must disabled at the edge termination region. Such a trench design typically leads to a compromised trade-off between process window and device performance. Other issues such as rounded corners are conventionally circumvented by sacrificial material deposit and each back. For example, an oxidized gate trench sidewall can be employed to regrow epitaxy silicon. However, the process is complex and increases manufacturing cost and development cycle (time-to-market).